搜索资源列表
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现,sdram verilog source code realizes
CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
FPGA-RAM-Verilog
- 用Verilog语言编写的FPGA，对波形数据用RAM存储-Using Verilog language FPGA, using the waveform data stored in RAM
ug_ram
- RAM design for FPGA in verilog
ram_Test
- RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
ram2
- RAm的 verilog描述，在Quartus中验证正确，可根据程序改成其他参数-Verilog descr iption of RAm in Quartus verify correct procedures can be changed in accordance with other parameters
RAM
- 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
ram_of_Fusion
- Fusion中的双口RAM编写，可以实现双向的调用。用Verilog编写。-Fusion in the preparation of dual-port RAM, you can realize a two-way call. Prepared using Verilog.
profiles
- source code of counter,ram,lfsr etc
RAM
- 用VerilogHDL写的ram程序，对初学者会有帮助。-Writing the ram with VerilogHDL procedures will be helpful for beginners.
planta_fagner
- is a test of a verilog implementation to do a oscilloscope with dual-port RAM
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
RAM
- 双口RAM Verilog描述 双口RAM Verilog描述-Dual-port RAM Verilog descr iption of dual-port RAM Verilog descr iption of dual-port RAM Verilog descr iption of
RAM
- Ram with 8 bits implemented in vhdl verilog code
RAM
- 单端口RAM，自己写的单端口RAM，同步写入同步读出，包括TESTBENCH和测试模拟文件-RAM
my_RAM
- pdf actel fpga verilog ram读写-pdf actel fpga verilog ram read and write
slave-ram-verilog
- ram代码 用verilog写的，有文字说明-verilog code of ram
ram
- verilog 编写的ram代码，开发环境为quartus-ram write verilog code development environment for quartus
ram
- 用verilog实现32字节8位RAM（触发器和M4K），用LPM实现RAM-32-byte by 8-bit verilog RAM (triggers and M4K), achieved by LPM RAM
Complete-RAM
- ram 64KB designed by haneesh in verilog